The present invention relates generally to a semiconductor integrated circuit device and a method for designing the same, and more specifically to a semiconductor integrated circuit device that include insulated gate field effect transistors (IGFETs) (such as Metal-Oxide-Semiconductor (MOS) FET (Field Effect Transistor)) and a method of designing the same.
As semiconductor device features becomes finer and the integration of such devices increases, an important concern can be electrostatic discharge (ESD). Electrostatic discharge can result when a static electricity, or the like, is discharged into or from a semiconductor device. ESD may result in damage to a semiconductor device, causing such a device to immediately fail, or have decreased reliability. One particular failure mechanism can be a breakdown of the gate dielectric in an insulated gate field effect transistor, such as the gate oxide of a metal-oxide-semiconductor FET.
ESD is believed to occur at various stages in a manufacturing process when semiconductor devices are handled and transported, for example.
Various models of the ESD breakdown phenomenon have been proposed, including a human body model (Human Body Model: HBM), a machine model (Machine Model: MM), and a charged device model (Charged Device Model: CDM).
In the HBM model, electric charges are generated, and then discharged to a device when a charged human makes contact with the device. In the MM model, electric charges are generated on a metal instrument, or the like, and then discharged to a semiconductor device when the instrument and device contact one another. In general, such a metal instrument can have a larger electrostatic capacitance than a human body, but also have a lower discharge resistance than a human body.
Using the above-mentioned models, semiconductor devices may be appraised for resistance/susceptibility to ESD events. For appraisal according to HBM and MM models, electric charges can be applied between two predetermined terminals of a device. In contrast, for appraisal according to a CDM model, a package and a chip of the device can be charged with electricity. Such charge can then be discharged to an outside location through terminals of the device.
To better understand the present invention, conventional approaches to semiconductor devices and ESD protection will be described below, including descriptions of a CDM model and a general counter measure to CDM type events.
Referring now to FIG. 15, an example of a semiconductor integrated circuit device is shown in a block diagram and designated by the general reference character 100. FIG. 15 shows various terminals and an internal circuit of a semiconductor integrated circuit device 100.
As illustrated in FIG. 15, a semiconductor integrated circuit device includes a terminal 110 that is connected with a gate of a MOSFET 112 through an input resistance Rin 114. A MOSFET 112 is illustrative of an internal circuit of a semiconductor device 100. An input resistor 114 is illustrative of an input resistance and an input wiring resistance inherent in semiconductor device 100.
A semiconductor device 100 also includes an electrostatic protective device, referred to herein as a clamping device 111. A clamping device 111 is connected between terminal 110 and reference electric potential wiring 117. A reference electric potential wiring 117 can be a ground (GND) wiring and/or a substrate electric potential wiring that may be operated at a different potential than GND. Electrostatic protective device 111 serves to prevent MOSFET 112 from being subjected to static electricity that is applied from the outside to terminal 110. Such static electricity may result in a MOSFET 112 being damaged.
Electrostatic protective device 111 is generally provided to protect the semiconductor device 100 from the aforementioned human body model (HBM) and machine model (MM) type events. The structure and size of electrostatic protective device 111 are selected to sufficiently insulate the semiconductor device 100 from HBM and MM type ESD events.
Referring again to FIG. 15, a capacitor 120 is also shown. A capacitor 120 can designate the equivalent capacitance of a semiconductor device 100 with respect to earth GND, when such a semiconductor device is being tested according to the CDM model. Electric charges with a semiconductor device may be stored on a capacitor 120.
During a test, terminal 110 is grounded through a CDM test switch 121. In the CDM test, electric charges on the device (i.e., all electric charges over the entire chip) are discharged to ground from terminal 110, through reference electric potential wiring 117 and electrostatic protective device 111. Reference electric potential wiring 117 includes reference electric potential wiring resistance Rg 116.
In addition, during a CDM type test, charge stored on a gate of MOSFET 112 can be discharged from terminal 110 to the ground. As noted above, charge on a gate of MOSFET 112 can constitute the charge on an internal circuit of a semiconductor device 100. The electric charge stored on the gate of MOSFET 112, that constitutes that of an internal circuit, can be substantially less than the charge discharged through the reference electric potential wiring 117. Consequently, charge on the gate of MOSFET 112 can be discharged to ground in a relatively shorter time that a reference electric potential wiring 117.
Such a faster discharge time may result in a relatively large electric potential developing between a gate of MOSFET 112, which has been discharged, and a source of MOSFET 112, which may be at the still discharging potential of reference electric potential wiring 117. Unless addressed, such an electric potential may breakdown the gate oxide film of a MOSFET 112, or otherwise damage a MOSFET 112.
To preventing such a breakdown there is generally provided a CDM protective device, also referred to as clamp device 113, that is in close vicinity to a MOSFET 112, between the gate and source of MOSFET 112.
A prior art technique for addressing ESD is shown in Electrical Overstress/Electrostatic Discharge Symposium Proceeding September 27-29, pp.220-227, 1988, referred herein as Reference 1. Reference 1 discloses that an input resistance, such as that shown as Rin 114 in FIG. 15, is effective for addressing HBM and MM type ESD events.
It is noted that an increase of an input resistance, such as Rin 114 in FIG. 15, may adversely affect circuit performance. Thus, there can be a tradeoff relationship between ESD protection and circuit performance. For this reason, it can be necessary to select an optimum value of an input resistance, Rin 114, that accounts for such a tradeoff relationship.
Additional prior art techniques are shown in Electrical Overstress/Electrostatic Discharge Symposium Proceeding, pp. 116 to 123, 1999 (referred to herein as Reference 2). Reference 2 discloses a relationship between an input resistance, such as Rin 114 of FIG. 15, a reference electric potential wiring resistance, such as Rg 116 in FIG. 15, and CDM insulation.
Referring now to FIG. 16, a simulation result of ESD for a device, such as that shown in FIG. 15 is shown. FIG. 16 shows how an electric potential difference (Vox) between the gate and the source of MOSFET 112 can vary over time during an ESD event. In particular, FIG. 16 shows how the electric potential differences (Vox) changes in response to the action of CDM protective device 113 during CDM testing. Three curves are shown; curves (a) to (c).
Curve (a) shows a change in Vox when CDM protective device 113 is completely clamped. The response of Vox is shown to sharply change in curves (b) and (c) as the operation of CDM protective device 113 varies. Curve (c) in particular demonstrates a Vox response where MOSFET 112 is destroyed during the CDM test.
It is noted that the value of Vox that can result in the destruction of a MOSFET 112 varies according to such factors as the thickness of the gate oxide film of a MOSFET 112.
Generally, semiconductor device resistance to CDM type events can be increased as an input resistance, such as Rin 114, is increased and reference electric potential wiring resistance, such as Rg 116, is decreased.
While an input resistance and reference electric potential wiring resistance can effect how a semiconductor device responds to CDM type events, the value of such resistances may be limited by circuit design considerations. For example, maximum values of an input resistance, such as Rin 114, and a reference electric potential wiring resistance, such as Rg 116, can be based upon an allowable range corresponding to overall circuit characteristics. Circuit simulation can determine such a range.
It is further noted that an input resistance (like Rin 114) can have a minimum value determined on the basis of HBM and MM test results. In addition, a reference electric potential wiring resistance (like Rg 116) can have a minimum value determined according to the layout of a semiconductor device.
Other prior art techniques are known that include constructing a testing device to perform actual ESD tests. The results of the test are reflected on the design of the actual device. In such cases, the structure of an electrostatic protective device (such as 111) and a CDM protective device (such as 113) can both being determined. Such devices may be repeated in size and structure for all input terminals and output terminals of a semiconductor device.
While numerous approaches to ESD protection have been described, a problem remains in conventional semiconductor devices and methods of design. The problem arises from variations in a reference electric potential wiring resistance (such as Rg 116). These variations may occur when a reference electric potential wiring is commonly connected with electrostatic protective devices and circuit devices such as MOSFETs, or even cases where a reference electric potential wiring is independently connected with electrostatic protective devices and circuit devices.
A specific example describing variations in the resistance of a reference electric potential wiring will now be described with reference to FIG. 17. FIG. 17 shows a semiconductor integrated circuit device that includes a reference electric potential wiring 117 that is commonly connected to electrostatic protective devices 111a to 111c. Electrostatic protective devices (111a to 111c) and commonly connected wiring 117 may also be connected to MOSFETS 112a to 112c included within internal circuits 150a to 150c. Internal circuits (150a to 150c) include CDM protective devices 113a to 113c. Further, each internal circuit (150a to 150c) may correspond to an input/output (I/O) terminal 110a to 110c. 
In the arrangement of FIG. 17, a reference electric potential wiring resistance Rg can vary according to the position of an I/O terminal (110a to 110c) and the position of a corresponding the internal circuit (150a to 150c). Such a variation arises due to differences in wiring lengths of reference electric potential wiring 117 for various different circuits. In particular, wiring lengths between points N1a and N2a, may be different from a length between points N1b and N2b, which may be different from that between points N1c to N2c. This can result in correspondingly different reference electric potential wiring resistances Rg.
Yet another example for showing how a reference electric wiring potential Rg can vary is shown in FIG. 18. In FIG. 18, a conventional semiconductor integrated circuit device is shown that includes a reference electric potential wiring 118 that is connected to electrostatic protective devices 111a to 111c, and a ground electric potential wiring 119 for MOSFETs 112a to 112c. MOSFETs (112a to 112c) may be representative of internal circuits (150a to 150c) of a semiconductor device. Internal circuits (150a to 150c) include CDM protective devices 113a to 113c. In FIG. 18, the reference electric potential wiring 118 and ground electric potential wiring 119 are constructed with separate wiring branches from GND terminal 115.
In the arrangement of FIG. 18, a difference in reference electric potential wiring resistance Rg can depend upon the distance between I/O terminals 110a to 110c and GND terminal 115. Even more particularly, a reference electric potential wiring resistances Rg in FIG. 18 can be the wiring resistance between electrostatic protective devices (111a to 111c) and respective MOSFETs 112a to 112c of the internal circuit, in which wiring paths passing through a branch point NO are considered.
Thus, in FIG. 18, reference electric potential wiring resistances Rg for I/O terminal 110a can vary according to a wiring resistance of the path N1a-N0-N2a, Rg for I/O terminal 110b can vary according to a wiring resistance of the path N1b-N0-N2b, and Rg for I/O terminal 110c can vary according to a wiring resistance of the path N1c-N0-N2c. 
The case of FIG. 18 can differ from that of FIG. 17, in that a difference between CDM withstand amounts at input and output terminals can be more conspicuous.
Conventionally, a size of CDM protective devices (such as 113a to 113c of FIGS. 17 and 18) can be initially estimated with a test device. For redundancy in the formation of such devices, an actual CDM protective device size can be larger than such an initial estimation. Further, once a size of a CDM protective device is determined, the same size CDM protective device can be used for all input and output terminal of a semiconductor device. This can limit a layout of an internal circuit.
In light of the above discussion, it would be desirable to arrive at some way of providing a semiconductor integrated circuit device with flexibility in layout, while at the same time maintaining certain circuit characteristics, and providing a predetermined CDM withstand amount at all I/O terminals.
It would also be desirable to provide a method of designing a semiconductor integrated circuit device that gives flexibility in layout, while at the same time maintaining certain circuit characteristics, and providing a predetermined CDM withstand amount at all I/O terminals.
A semiconductor integrated circuit device according to the present invention may include insulated gate field effect transistors (IGFETs) (such as metal-oxide-semiconductor FETs, or MOSFETs) having gates connected to input/output (I/O) terminals through a first resistance. First clamping devices can be connected to each I/O terminal. Second clamping devices can be connected between the gate and source of each IGFET. First and second clamping devices associated with the same I/O terminal can be connected to one another through a second resistance.
According to one aspect of the embodiments, second clamping devices corresponding to different I/O terminals can have different capabilities.
According to another aspect of the embodiments, first resistances corresponding to different I/O terminals can be varied to establish a maximum second-to-first resistance ratio.
A method of designing a semiconductor integrated circuit device according to the present invention can include designing an electrostatic protective circuit and a protective device for a semiconductor integrated circuit device that includes an IGFET provided on a semiconductor substrate. According to a method of the present invention, a simulation may be performed on a predetermined CDM test equivalent circuit. Such a test circuit may include a first clamping device connected to an I/O terminal, a first IGFET having a gate connected to the I/O terminal through a first resistance, a second clamping device connected between a gate electrode and source drain electrode of the first IGFET, and the first and second clamping devices being connected to one another through a second resistance.
From such simulation results, a ratio between the second resistance and first resistance can be determined such that an electric potential difference between the gate electrode of the first IGFET and the source or substrate electrode of the same does not exceed a predetermined value.
In accordance with the present invention, flexibility of a layout may be provided without losing circuit characteristics. Further, a same CDM withstand amount may be maintained between I/O terminals. In this way, a semiconductor integrated circuit device having satisfactory CDM withstand amounts at all input and output terminals may be provided.
In addition, according to the present invention a design for a semiconductor integrated circuit device having a satisfactory CDM withstand amount can be effectively and accurately achieved.